Download Logic Design and Verification Using SystemVerilog (Revised), by Donald Thomas
Download Logic Design and Verification Using SystemVerilog (Revised), by Donald Thomas
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Logic Design and Verification Using SystemVerilog (Revised), by Donald Thomas
Download Logic Design and Verification Using SystemVerilog (Revised), by Donald Thomas
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About the Author
Donald Thomas is Professor Emeritus of Electrical and Computer Engineering at Carnegie Mellon University where he has taught logic design, RT-level design, design languages (Verilog and SystemVerilog), verification, and computer-aided design algorithms for the design of integrated circuits and systems.
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Product details
Paperback: 336 pages
Publisher: CreateSpace Independent Publishing Platform; Revised edition (March 1, 2016)
Language: English
ISBN-10: 1523364025
ISBN-13: 978-1523364022
Product Dimensions:
7.4 x 0.8 x 9.7 inches
Shipping Weight: 1.4 pounds (View shipping rates and policies)
Average Customer Review:
4.8 out of 5 stars
7 customer reviews
Amazon Best Sellers Rank:
#642,274 in Books (See Top 100 in Books)
This is a really great book, covering a significant gap in most curriculum: whatever happens after the intro digital logic class. This book takes your SystemVerilog skills to the next level.Most significant digital systems will have many interacting, cooperative FSMs. How do you design for cooperation? How do you interface them together? And, most importantly, how do you test them as a system? These are the major themes of this book. Specific topics include: interfaces, hardware threads, interactions among those thread (synchronous and asynchronously), testbenches, randomization in the testbench, concurrent assertions, and measuring functional coverage.The book also presents a deep model of the simulation kernel, showing what it does during the many different phases of each simulation cycle. You'll always be able to answer the questions about why your testbench needs "<=" and just what the "program" keyword is.The revised edition squashed quite a few typos!Overall, this is an excellent book that doesn't really have any competition.Disclaimer: I have had the pleasure of teaching with the author for several years, using this text for our classes. That means I've read the book cover-to-cover several times!
Not sure if there's a more in-depth (System)Verilog reference that could be comprehended by a hobbyist at their own pace.
Very Good book for beginners
Perhaps this is one of very few SystemVerilog books make it progressive and comprehensible!
classic verilog book
I have been teaching digital design for over 25 years and while introductory texts are a dime a dozen, finding an appropriate text for our “advanced†course has been a perennial challenge, as the course is focused on using an HDL for synthesis and verification, not VLSI or computer architecture.After using a very expensive book to teach SystemVerilog, Don Thomas’ book was a welcomed relief to my students wallets and far more understandable. In addition to the attractive price, it has just about the right amount of review to refresh the memories of those who took the introductory course two years earlier while providing plenty of new material, particularly Part II (Hardware Threads) and Part III (Testbenches). Those sections are a fantastic at supporting topics that previously I had to develop materials. At the end of the semester I surveyed the students as to whether they felt the book was useful. While there are always some who reply “never read it†– and a few who wished they had earlier! – those who did use the book found it very helpful for completing the projects.That said, there are a few ways the book could be improved, starting with the index. Several students indicated that it was difficult to find what they were looking for, particularly when trying to understand more complex examples from later in the book which use constructs that were presented much earlier. However, part of this is my fault for not enforcing a strict schedule of reading assignments. All in all, the book is a very valuable addition to my course and I plan to required it each year for the foreseeable future.
This book is an excellent resource for anyone working with System Verilog. Don't be fooled by the clear writing---this book provides a detailed description of System Verilog that serves as an excellent source for anyone working on a significant System Verilog project. The book also has great introductory material and extensive examples but it goes beyond introductory material to give the details needed to use SV as a tool.
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